The technical meeting is jointly sponsored by the  IEEE Rochester Computer Society Chapter and Student Branch Chapter of RIT

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IC Chip Design and Verification

Matt Genovese, Senior Verification Engineer, Freescale Semiconductor

Time: 6 PM – 7:15 PM

Date: Thursday, December 7, 2006

Place: Xerox Auditorium, KGCOE, Rochester Institute of Technology, Rochester, NY 14623

Parking: Parking lots JF, JG, and JH

RSVP by Wednesday, December 6, 2006: Please call for head count for pizza and drink

Please call: Mr. Samuel Fryer, Eastman Kodak at 588-8489

                    Dr. Kenneth W. Hsu, RIT at 475-2655

Abstract

Freescale Semiconductor Inc. (formerly Motorola) has developed a methodology for verification over the past ten years. It evolved from the Somerset PowerPC partnership between IBM and Motorola, and has been used on countless processors and SoC’s to date. The methodology focuses on achieving certain goals, such as verification IP reuse, reducing time required for overall verification, increasing efficiency of engineering effort for finding bugs, reducing overhead in simulations, and acquiring real-time coverage data to feedback to engineers during verification. The purpose of the talk is to summarize this methodology for a potential audience of inexperienced as well as seasoned verification engineers, discussing the rationale of verification flow, and how these mentioned goals are met. In terms of simulation-based verification, the test-bench architecture, types of test case, management of verification will be covered. The non-simulation alternatives in functional verification are covered as well.

Speaker Biography

Matt Genovese is an experienced Design Verification engineer at Freescale Semiconductor in Austin, Texas.  He has spent the past five years in the PowerPC Design Center verifying both cores and SoC’s, developing testbenches, piloting new verification tools, and helping to define and refine the corporate verification methodology.  He has a particular interest in assertion-based verification, and closing the gap between architectural definition and functional verification.  Prior to this position, Matt spent four years as a lead Product & Test Engineer at Motorola.  He received a B.S. degree in Computer Engineering from the Rochester Institute of Technology, and holds a M.S. degree in Electrical Engineering from the University of Texas at Austin. He is a member of the Industrial Advisory Board of the Department of Computer Engineering at RIT.